This section of the MIG Design Assistant focuses on Simulation of the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
MIG provides all files needed to simulate the memory interface in the output 'example_design/sim' and 'user_design/sim' directories. Included is:
Simulation testbench - sim_tb_top.v/.vhd
Memory models (provided for Micron only and only if License Agreement is accepted in the MIG tool)
ModelSim do script to run the functional simulation - sim.do
NOTE: At this time, timing simulation is not supported.
Speeding Up Simulation
Specific parameters are available to speed up simulation times. For more information, please see: