AR# 34308: MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met
MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met
The first step in debugging issues encountered in hardware testing is to verify that the pin-out and banking requirements of the Virtex-6 DDR2/DDR3 design have been followed. These guidelines can be found on the Description tab of the Bank Selection screen within the MIG tool, as well as in the Design Guidelines sections within the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406): http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
If the MIG output design was not modified, these requirements will be followed.However, if any changes have been made to the UCF, these changes must be verified against the design requirements.
This Answer Record points to additional information on verifying any placement changes, as well as detailed information on design requirements that cause common questions.
Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
(Xilinx Answer 34383) - How to create a custom UCF or modify the MIG UCF ensuring all design requirements are followed? (Xilinx Answer 35085) - How many banks can the Virtex-6 DDR2/DDR3 design span? (Xilinx Answer 34317) - Usage of Inner Column for Address/Control Group (Xilinx Answer 34390) - Usage of Inner/Outer Columns for Data Group (Xilinx Answer 33268) - When using Multiple Controllers, is it possible to share MMCM resources? (Xilinx Answer 33607) - Is it possible to swap data bytes in the MIG output? (Xilinx Answer 34477) - Why does the UCF include pin prohibits and LOC constraints for capture (CPT) logic? Can these be moved? (Xilinx Answer 34540) - Why does the UCF include pin prohibits and LOC constraints for resynchronization (RSYNC) logic? Can these be moved? (Xilinx Answer 34543) - Do DQS pins need to be allocated on Clock Capable I/O (CCIO) pins? (Xilinx Answer 34570) - Is it possible to maximize the DDR groups within a bank for a single controller design? Includes information on splitting address/control across banks, removing memory interface signals (ie - DM), using Internal VREF, and DCI Cascade.
(Xilinx Answer 39067)- MIG Virtex-6 DDR2 - I cannot select BUFIO PINs in the dropdown list when creating a DDR2 MIG v3.6 design with AXI interface enabled. Why?