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AR# 34315

MIG 7 Series and Virtex-6 DDR2/DDR3 - Supported CORE Generator Options

描述

This section of the MIG Design Assistant focuses on Supported CORE Generator Options for 7 Series and Virtex-6 DDR3/DDR2 designs.

Below, you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).

The Xilinx MIG Solution Center is available to address all questions related to MIG.
 
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

For a complete list of supported CORE Generator options for Virtex-6 DDR3/DDR2 designs please refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started > Customizing and Generating the Core" and "DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started > Creating Virtex-6 FPGA DDR3 Memory Controller Block Design" sections in UG406: http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

For a complete list of supported CORE Generator options for 7 Series DDR3/DDR2 designs please refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started > Customizing and Generating the Core" and "DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started > Creating 7 Series FPGA DDR3 Memory Controller Block Design" sections in UG586: http://www.xilinx.com/support/documentation/ipinterconnect_mig-7series.htm 


If you are targeting Synplify Pro, ensure you select Synplicity in the CORE Generator Project Options. 

The RTL and project files generated by MIG will be different based on this selection.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34321 MIG 7 Series and Virtex-6 DDR2/DDR3 - Using the CORE Generator tool N/A N/A

相关答复记录

AR# 34315
日期 08/12/2014
状态 Active
Type 解决方案中心
器件 More Less
IP
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