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AR# 34321

MIG 7 Series and Virtex-6 DDR2/DDR3 - Using the CORE Generator tool

描述

This section of the MIG Design Assistant focuses on using the CORE Generator tool to generate 7 series and Virtex-6 DDR3/DDR2 FPGA designs. All MIG designs are generated using the Xilinx CORE Generator tool. Please select from the options belowto find information related to your specific question.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

For information on the supported devices for MIG 7 Series and Virtex-6 FPGA DDR3/DDR2 FPGAdesigns, see:
(Xilinx Answer 34314) - Supported Devices

For information on the supported CORE Generator system options for MIG 7 series and Virtex-6 DDR3/DDR2 FPGA designs, see:
(Xilinx Answer 34315) - Supported CORE Generator Options

For information on the MIG Output for 7 series and Virtex-6 DDR3/DDR2 FPGA designs, see:
(Xilinx Answer 34323) - MIG Output

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

子答复记录

相关答复记录

AR# 34321
日期 10/04/2012
状态 Active
Type 解决方案中心
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG
的页面