AR# 34323: MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output
MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output
This section of the MIG Design Assistant focuses on MIG Output for 7 Series and Virtex-6 DDR3/DDR2 designs. The MIG output includes rtl files for the MIG core, an example traffic generator, simulation testbench with the appropriate memory model instantiated, simulation and implementation script files, and a User Constraints Files (.ucf). These files allow users to quickly simulate the design to view functional behavior and create a bitfile to run the design in hardware. Please select from the below options to find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For a description of the MIG 7 Series and Virtex-6 DDR3/DDR2 design output directory and files, please see: (Xilinx Answer 34318)- Description of Output Directory/Files
For information on the MIG 7 Series and Virtex-6 DDR3/DDR2 Example Design, please see: (Xilinx Answer 34319)- Usage of Example Design
For information on the MIG 7 Series and Virtex-6 DDR3/DDR2 User Design, please see: (Xilinx Answer 34320)- Usage of User Design