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AR# 3436

FPGA Express - Cannot link cell '<cell>' to its reference design '<component>'. (FPGA-LINK-2)

Description

Keywords: FPGA Express, VHDL, Verilog, library, component, instantiation, linked

Urgency: Standard

General Description:
After creating an implementation for an HDL design which instantiates library
primitives or black boxes, the component is not linked to the design. The
following warning appears:

Warning: Cannot link cell 'design/component_instance' to its reference design
'library_component' (FE-LINK--2)
Warning: The cell '/top/component_instance' is not linked to any design
(FE-CHECK-4)

To verify this, right-click on the implementation and select "Edit Constraints."
Under the Modules tab, the word, "UNLINKED" appears before the instance name.

解决方案

1

FPGA Express library primitive declarations must be capitalized within VHDL.

For example, an AND2 gate will be an UNLINKED module when the following
declaration in a design is implemented:

component and2
port(I0, I1: in std_logic; O: out std_logic);
end component;

However, the following code in a design appears LINKED after implementation:

component AND2
port(I0, I1: in std_logic; O: out std_logic);
end component;

2

If the UNLINKED cell is a "black box", then the UNLINKED warning may be
safely ignored.

A black box is a component instantiation in your HDL code that is represented
by a netlist that will be merged by NGDBuild. This netlist may be EDIF, XNF, or
NGO, and must be supplied to NGDBuild along with the top level XNF file
written by FPGA Express.

DO NOT read XNF files into FPGA Express, as problems may arise when FPGA
Express tries to re-optimize carry logic.

Nothing special must be done within FPGA Express 2.0 to preserve this black box.

With FPGA Express 1.2, the module must be preserved. To do this, double-click
on the implementation to bring up the constraints GUI. Under the "Modules" tab,
under the "Hierarchy" column, set the module to "Preserve."
AR# 3436
创建日期 02/11/1998
Last Updated 08/11/2003
状态 Archive
Type 综合文章