AR# 34388


MIG Virtex-6 DDR2/DDR3 - How to generate a design using a fixed/custom pin-out


Starting with MIG 3.4, available with ISE 12.1, the Fixed Pin Out feature is available to allow users to run through the MIG tool once, select the desired pins, and upon verification of the selected pins against the design requirements, generate a MIG design.
For information on using this feature and on errors generated during the pin out verification, please see the Fixed Pin Out section in the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406):
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


To use the Fixed Pin Out feature, open the MIG tool and start creating the desired memoryinterface. The Extended FPGA Options page includes a Pin/Bank Selection Mode option at the bottom of the screen. The two options are:
  • New Design: Pick the optimum banks for a new design
  • Fixed Pin Out: Pre-existing pin out is known and fixed

If a pin-out is not already locked, Xilinx recommends using the New Design option. If however, the pin-out is locked, select the Fixed Pin Out option. This invokes the Pin Selector tool which lists all required interface signals and the corresponding Signal Group. Users then manually select the Bank and Pin numbers for each interface signals. A "Validate" option exists to verify the pin selections against the Virtex-6 FPGA design requirements. Upon core generation, a MIG design is output according to the input pins.
To learn more about the Pin Out and Banking Requirements of the MIG Virtex-6 FPGA DDR2/DDR3 design, see (Xilinx Answer 34308).



AR# 34388
日期 02/05/2013
状态 Active
Type 综合文章
器件 More Less
People Also Viewed