This section of the MIG Design Assistant focuses on Supported Data Widths for Virtex-6 DDR3/DDR2 designs. NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The Virtex-6 MIG DDR2/DDR3 memory controller supports data widths of up to 144 bits, in multiples of the base device's width, depending on the selected FPGA, FPGA speed grade, memory type, and specified frequency. MIG supports lower frequencies for data widths above 72-bits. For details on supported frequencies, see "Design Guidelines" in the Virtex-6 FPGA Memory Interface Solutions User Guide(UG406): http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
Xilinx does not have the ability to test every data width. Characterization is completed up to 72-bit data widths. Because of this, the supported frequency range is decreased for wider interfaces. If a customer wants to increase the frequency above this data width, all testing and characterization must be completed by the customer. Xilinx only supports the frequency ranges and data widths available through the MIG tool. It is important that customers focus on timing closure, IBIS simulation, and SI analysis. The timing is critical because the read data capture logic for wider interfaces spans more area of the device. IBIS and SI analysis are important as loading and general SI concerns increase with a wider memory interface.