This answer record contains the Release Notes and Known Issues for the Virtex-6 FPGA Connectivity Kit and its Targeted Reference Design.
The nature of this content is to help you avoid running into issues when performing intended operations with the kit.
The Virtex-6 FPGA Connectivity Kit v1.0 includes the following components:
Software:
The following versions of Virtex-6 FPGA Connectivity Kit Targeted Reference Design are available:
V6 Connectivity TRD |
Silicon |
ISE |
PCIe |
XAUI |
Memory Controller(MIG) |
v 1.0 |
CES |
11.4 |
v 1.3 |
v 9.1 |
v 3.3 |
v 1.1 |
CES |
12.1 |
v 1.3 + rev 1 patch |
v 9.1 |
v 3.4 |
v 1.1 |
Production |
12.1 |
v 1.5 |
v 9.2 |
v 3.4 |
v 1.2 |
CES |
12.2 |
v 1.3 + rev 2 patch |
v 9.1 |
v 3.5 |
v 1.2 |
Production |
12.2 |
v 1.5 |
v 9.2 |
v 3.5 |
v 1.3 |
CES |
12.3 |
v 1.3 + rev 2 patch |
v 9.1 |
v 3.6 |
v 1.3 |
Production |
12.3 |
v 1.6 |
v 9.2 |
v 3.6 |
v 1.0 with AXI4 protocol support |
Production |
12.3 |
v 2.1 |
v 9.2 |
v 3.6 |
v 1.4 |
CES |
12.4 |
v 1.3 + rev 2 patch |
v 9.1 |
v 3.6.1 |
v 1.4 |
Production |
12.4 |
v 1.6 |
v 9.2 |
v 3.6.1 |
v 1.1 with AXI4 protocol support |
Production |
12.4 |
v 2.2 |
v 9.2 |
v 3.6.1 |
v 1.2 with AXI4 protocol support |
Production |
13.1 |
v 2.3 |
v 10.1 |
v 3.7 |
v 1.3 with AXI4 protocol support |
Production |
13.2 |
v 2.4 |
v 10.1 |
v 3.8 |
v 1.4 with AXI4 protocol support |
Production |
13.3 |
v 2.4 |
v 10.1 |
v 3.9 |
v 1.5 with AXI4 protocol support |
Production |
13.4 |
v 2.5 |
v 10.2 |
v 3.91 |
To understand which version of the silicon you have, please see (Xilinx Answer 37579).
For all design versions prior to 13.1, the Virtex-6 GTX Transceiver - Delay Aligner Work-around might be required.
For more information, refer to (Xilinx Answer 39430), (Xilinx Answer 39456), and (Xilinx Answer 39492).
For all design versions before 13.2, the TRCE/Timing Analyzer tools have not correctly analyzed the Virtex-6 36Kb block RAM (RAMB36E1),18Kb RAM(RAMB18E1), and 18Kb FIFO (FIFO18E1) control signals when used in SDP, TDP, or ECC modes.
This can potentially result in unreported setup and hold time violations.
The unreported violations might result in read and write errors.
For more information, refer to (Xilinx Answer 42444).
Virtex-6 FPGA Connectivity Kit TRD v1.0 for ISE 11.4 with CES Silicon
ISE 11.5 is not supported. Do not upgrade to 11.5. Check (Xilinx Answer 34432) for updates.
Virtex-6 FPGA Connectivity Kit TRD v1.1 for ISE 12.1 with CES Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.1 for ISE 12.1 with Production Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.2 for ISE 12.2 with CES Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.2 for ISE 12.2 with Production Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.3 for ISE 12.3 with CES Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.3 for ISE 12.3 with Production Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.0 with AXI4 Protocol for ISE 12.3 on Production Silicon
Virtex-6 Connectivity Kit TRD v1.4 for ISE 12.4 with CES Silicon
Virtex-6 Connectivity Kit TRD v1.4 for ISE 12.4 with Production Silicon
Virtex-6 FPGA Connectivity Kit TRD v1.1 with AXI4 Protocol support for ISE 12.4 on Production Silicon
Virtex-6 Connectivity Kit TRD v1.2 with AXI4 Protocol support for ISE 13.1 on Production Silicon
Virtex-6 Connectivity Kit TRD v1.3 with AXI4 Protocol support for ISE 13.2 on Production Silicon
The Windows driver has been tested and works on Windows XP-32bit systems (English, SP3). Support on Windows 7, 64-bit systems and other flavors of Windows XP is not yet available.
If the windows driver source code is modified, the drivers need to be recompiled.Virtex-6 Connectivity Kit TRD v1.4 with AXI4 Protocol support for ISE 13.3 on Production Silicon
The Windows driver has been tested and works on Windows XP-32bit systems (English, SP3). Support on Windows 7, 64-bit systems and other versions of Windows XP is not yet available.
Virtex-6 Connectivity Kit TRD v1.5 with AXI4 Protocol support for ISE 13.4 on Production Silicon
The Windows driver has been tested and works on Windows XP-32bit systems (English, SP3). Support on Windows 7, 64-bit systems and other versions of Windows XP is not yet available.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
43750 | Xilinx 电路板和套件解决方案中心 — 热门问题 | N/A | N/A |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
44362 | The Application GUI on a Linux machine does not load successfully (13.2; v1.3) | N/A | N/A |
43097 | Virtex-6 FPGA Connectivity Kit TRD - The PlanAhead Flow on a 32-bit OS Does Not Meet Timing | N/A | N/A |
34657 | Virtex-6 FPGA Connectivity Kit TRD - PCI-e only trains to Gen1 | N/A | N/A |
34655 | Virtex-6 FPGA Connectivity Kit TRD - DDR3 fails to initialize | N/A | N/A |
34654 | Virtex-6 FPGA Connectivity Kit TRD - How do you change the default XAUI buffer size? | N/A | N/A |
34652 | Virtex-6 FPGA Connectivity Kit TRD - TRD Uses Custom MIG Files | N/A | N/A |
34651 | Virtex-6 FPGA Connectivity Kit TRD - Block RAM Utilization | N/A | N/A |
AR# 34432 | |
---|---|
日期 | 01/26/2015 |
状态 | Active |
Type | 已知问题 |
器件 | |
Boards & Kits |