Prior to ISE tools 12.1, the Spartan-6 FPGA RAMB8BWER component could be set to RAM_MODE=SDP and accept any data WIDTH value on either port. Due to an unexpected hardware issue, only the 36-bitdata widthon both ports is now supported in this mode. Failure to set both ports to 36-bits (DATA_WIDTH_A == DATA_WIDTH_B == 36) results in a functional failure that appears as data corruption from any read from the block RAM. Currently (prior to 12.1), there are no warnings about this behavior in the software; all port widths are accepted in SDP mode.
RAMB8BWER with RAM_MODE set to "SDP" and WIDTH_A and/or WIDTH_B not set to 36.Additionally, the RAM_SDP_MACRO can exhibit this when BRAM_SIZE="9Kb", and one port is greater than 18-bits and one port is 18-bits or less. Currently, XST synthesis behavior is being reviewed to confirm that it does notcreate this situation.It is unknown how other synthesis tools behave with respect to this issue.
Software Version Information
Any design instantiating a RAMB8BWER with RAM_MODE set to SDP must have both A and B ports set to 36. In cases where that is not possible, the following can be done to work around the issue:
The Spartan-6 FPGA Block RAM Resources User Guide (UG383) includes a complete guide to port width combinations in Tables 1, 2, and 3. Please refer to UG383 for more information on this issue, and all other information regarding Spartan-6 FPGA block RAM.