2. 技术支持
  3. AR# 3454: Foundation F1.3/F1.4, XVHDL, Synthesis, grayed, Error: Hde: Foundation option in xilinx, Keylock not found. (Sentinel driver)
  4. AR# 34541: Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM Simple Dual Port (SDP) Data Width Restriction

AR# 34541

Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM Simple Dual Port (SDP) Data Width Restriction

描述

Spartan-6 FPGA 9K block RAM in SDP mode does not support all port width combinations.

解决方案

Issue Description

Prior to ISE tools 12.1, the Spartan-6 FPGA RAMB8BWER component could be set to RAM_MODE=SDP and accept any data WIDTH value on either port. Due to an unexpected hardware issue, only the 36-bitdata widthon both ports is now supported in this mode. Failure to set both ports to 36-bits (DATA_WIDTH_A == DATA_WIDTH_B == 36) results in a functional failure that appears as data corruption from any read from the block RAM. Currently (prior to 12.1), there are no warnings about this behavior in the software; all port widths are accepted in SDP mode.

Affected Components

RAMB8BWER with RAM_MODE set to "SDP" and WIDTH_A and/or WIDTH_B not set to 36.Additionally, the RAM_SDP_MACRO can exhibit this when BRAM_SIZE="9Kb", and one port is greater than 18-bits and one port is 18-bits or less. Currently, XST synthesis behavior is being reviewed to confirm that it does notcreate this situation.It is unknown how other synthesis tools behave with respect to this issue.

Software Version Information

  • ISE Design Suite 11.5 and earlier - No error or warning occurs.Simulation behavior looks normal. Hardware can exhibit functional failures (data corruption) during reads.
  • ISE Design Suite 12.1 and later - Design Rule Checks (DRCs) have been added to the UNIMacro, UNISIM, Map and Physical DRCs to error outif an illegalsetup is detected.

Work-arounds

Any design instantiating a RAMB8BWER with RAM_MODE set to SDP must have both A and B ports set to 36. In cases where that is not possible, the following can be done to work around the issue:

  • If both ports are 18-bits or less, use the RAMB8BWER in RAM_MODE=TDP mode and connect as SDP
  • If the write port is 18-bits or less and the read port is 36 bits, you can set both port widths to 36-bits, RAM_MODE=SDP and use the byte-write enables to select the appropriate byte(s) to write.
This has minimal affect on area and performanceand is therefore the generallypreferred method. If this cannot be done, the alternative is to use a RAMB16BWER.
  • If the read port is 18-bits or less and the write port is 36-bits, it is suggested to use a RAMB16BWER when performance is needed. If low on block RAM resources, a RAMB8BWER can be used in SDP mode with both ports set to 36-bits. However, the output would need to be MUXed to index the appropriate word(s) to the output.



Documentation

The Spartan-6 FPGA Block RAM Resources User Guide (UG383) includes a complete guide to port width combinations in Tables 1, 2, and 3. Please refer to UG383 for more information on this issue, and all other information regarding Spartan-6 FPGA block RAM.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
32651 Spartan-6 — ISE 软件 11 与 Spartan-6 FPGA 有关的已知更新问题 N/A N/A
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
46792 Spartan-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems N/A N/A
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
32651 Spartan-6 — ISE 软件 11 与 Spartan-6 FPGA 有关的已知更新问题 N/A N/A
AR# 34541
日期 11/15/2012
状态 Active
Type 设计咨询
器件
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