AR# 34712


Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect


Initialization of the 9Kb block RAM in SDP mode is not correctly performed in ISE Design Suite 11.5. This issue has been fixed in ISE software12.1 and later.


Issue Description

When using the 9K block RAM in SDP mode with ISE 11.5 and earlier software, the block RAM might not have the proper memory array initialization values.When attempting to initialize to anything but the default of all zeros, the actual initialized value in the block RAM might not be as expected.

Affected Components

RAMB8BWER in SDP mode with INITs or INIT_FILE set to anything but the default all zeros.This can also occur via synthesis inference, use of UNIMacro block RAM components, use of memory generator with a COE file, and the use of some cores that contain the affected block RAM.

Software Affected

  • InISE Design Suite11.5 and earlier- Simulation andFPGA Editorshow proper INIT strings, however, the data placed into the block RAM can appear corrupt. Hardware testing is the only valid way to determine if initializationhas occurred correctly.
  • In ISE Design Suite12.1 and later - This issueisresolved in the 12.1 version ofthe ISE software.9K block RAM initializes correctly, and is reflected in simulation and FPGA Editor views.


There is no work-around in the ISE 11.5 and earlier software.Until a fix is available in ISE 12.1, avoid initializing the RAMB8BWER to anything except for all zeros.

Note: There are other issues that might affect your design while using the Spartan-6 Block RAM in this configuration.Please see (Xilinx Answer 32651) in the Block RAM section for all known issues, including other initialization issues and a port width restriction for 9K block RAM in SDP mode.



Answer Number 问答标题 问题版本 已解决问题的版本
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A


AR# 34712
日期 11/15/2012
状态 Active
Type 设计咨询
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