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AR# 34735

Design Assistant for PCI Express - Do VHDL customers need a mixed language license to simulate the integrated block and tranceiver models


This answer record identifies starting points when debugging hardware related issues to PCI Express.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


Xilinx SecureIP is delivered using Verilog LRM - IEEE Std 1364-2005 to encrypt the hard block. For PCI Express simulations this includes the models for the PCIe block and the transceivers. These Verilog models do require a Verilog simulation license. Customers who are simulating already with a Verilog license are fine. After running compxlib to compile the libraries, simulate as usual.

For ModelSim users, current versions of ModelSim allow simulating the encrypted models without having to purchase a full mixed-mode license. For ISE 11 series software, users can download what are called marked secure Verilog library files from (Xilinx Answer 33118). Using these, ModelSim VHDL user do not have to purchase a Verilog license. As long as the design RTL and endpoint wrapper is VHDL as delivered with the Virtex-6 and Spartan-6 FPGA cores and the marked libraries are used, users can simulate the PCIe and MGTs with a VHDL license only.

Note that MTI PE users will have to update their swift License to the new SecureIP Op software license feature. Refer to your local Mentor Graphics sales office for more information about how to go from existing SWIFT Op software to SecureIP Op software in order to enable this functionality. ModelSim SE VHDL customers do not require a new license feature. In ISE 12.1 software, these marked IP will be included by default and you will no longer have to download them.

NC-Sim and VCS already provide a mixed-mode license to Xilinx users by default and no further action is needed other than running compxlib.

For Virtex-5 FPGA Block Plus users, refer to (Xilinx Answer 34183) which describes how to create an NGC from the Verilog provided wrapper source. Users can then run NETGEN to turn the ngc file into a VHDL model.

Revision History
08/13/2010 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
36207 Design Assistant for PCI Express - Simulation Set-Up and Licensing Questions N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 34735
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less