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AR# 34740

MIG Virtex-6 DDR2/DDR3 - PHY Initialization and Calibration

描述

The PHY logic contains state logic for initializing the SDRAM memory after power-up and performs timing training of the read and write data paths to account for system static and dynamic delays.This section of the MIG Design Assistant focuses on the initialization and calibration (timing training) performed by the PHY at power-up.

The Virtex-6 Memory Interface Solutions User Guide (UG406)includes a detailed section on the PHY logic.Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture >PHY section:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The following diagram shows the Virtex-6 PHY sequence for initialization and calibration:

When calibration completes successfully cal_done asserts. For detailed information on each stage, see the following:

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
35094 MIG Virtex-6 and 7 Series DDR3 - Write Leveling N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35163 MIG 7 Series and Virtex-6 DDR2/DDR3 - Per-Bit Deskew N/A N/A

相关答复记录

AR# 34740
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP
的页面