AR# 34763


MIG Virtex-6 and 7 Series DDR2/DDR3 User Interface - Performing Reads


This part of the MIG Design Assistant will guide you to information on performing reads from the User Interface (UI).

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Read Data on the User Interface

The read data is returned by the UI in the requested order and is valid when app_rd_data_valid is asserted.


  • The MIG controller presents a flat address space to the user interface and translates it to the addressing required by the SDRAM.
  • The MIG controller supports sequential and interleaved reads.
  • The burst order for a sequential read with BL=8 will start at the column address specified and increment sequentially but wrap around after address 3 and 7. The burst is divided into the top 4 and bottom 4 address locations. For example, for a Column Address of 011, the data returned will follow the sequence 3,0,1,2,7,4,5,6. While, for a Column address of 101, the data returned will follow the sequence 5,6,7,4,1,2,3,0. This adheres to the JEDEC Standard.
    • For more information on sequential and interleaved burst, see DDR2 SDRAM Standard JESD79-2C (Table 9), or DDR3 SDRAM Standard JESD79-3 (Table 3).
  • For a burst chop of 4 (DDR3 only), there will be four cycles of valid data followed by four cycles of invalid data. For more details on burst addressing, see the DDR3 JEDEC Standard.

Additional Information

For timing diagrams and more information, see the DDR2 and DDR3 Memory Interface Solution > Interfacing to the Core > Read Path section in the Virtex-6 Memory Interface Solutions User Guide and the 7 Series FPGAs Memory Interface Solutions User Guide. These guides include examples for all burst lengths along with back-to-back operation.




AR# 34763
日期 09/26/2013
状态 Active
Type 解决方案中心
器件 More Less
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