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AR# 3477

Foundation Express 2.0: Module compile inserts STARTUP and clock buffers (BUFG)


Keywords: Foundation, FPGA Express, VHDL, Verilog, Startup, Module

Urgency: Standard

General Description:
When compiling a design as a module (by checking the "Do Not Insert I/O" box),
Express will still insert the STARTUP module and BUFG components if it sees
fit to do so. This will become a problem as modules are brought together under
the top level design, as too many resources will be used.


This issue has been fixed by Synopsys by patch version 2.0.3. This patch can
be downloaded from the Xilinx or Synopsys FTP site (depending on the version
of Express you have). Details are given in (Xilinx Solution 3566).
AR# 3477
日期 08/19/1999
状态 Archive
Type 综合文章