AR# 34793


12.1 PlanAhead - Synthesis fails with a netlist as top level in an RTL Project


After starting in an RTL Flow in the PlanAhead tool, when I remove the top level HDL module and replace it with an EDIF top level module, XST fails.

Why is this happening?


If you created a project with RTL sources and try to replace the top_level with an EDIF file, synthesis fails with no messages.

If the top level source type of your design has changed, you need to create a new Netlist Project.

Improved messaging has been implemented in ISE Design Suite 12.2.

AR# 34793
日期 05/23/2014
状态 Archive
Type 已知问题
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