AR# 34882

MIG Design Assistant - Virtex-6 Synthesis and Implementation Debug Guide

描述

This section of the MIG Design Assistant focuses on Synthesis and Implementation of the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

For a complete list of Synthesis and Implementation debugging for Virtex-6 DDR3/DDR2 designs, please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Synthesis and Implementation Debug" section of UG406:

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34285 MIG Design Assistant - Virtex-6 Synthesis and Implementation N/A N/A
AR# 34882
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP