AR# 34883

MIG Virtex-6 DDR2/DDR3 - Debugging issues with User Design simulations

描述

This section of the MIG Design Assistant focuses on simulation debug for a User Design simulation with Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

For a complete list of simulation debug steps for Virtex-6 DDR3/DDR2 designs please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Simulation Debug"=>"Debug Issues with User Design Simulation" section of UG406:

Most user design simulation issues are related to incorrectly driving the User Interface. It's important to understand how to do so properly. For additional information on interfacing the core please refer to the"Interfacing to the Core"=>"Simulation Debug"=>"User Interface" section of UG406:

(Xilinx Answer 33698)- Driving User Interface

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34284 MIG Design Assistant - Virtex-6 DDR2/DDR3 Simulation N/A N/A
34884 MIG Virtex-6 DDR2/DDR3 - Simulation Debug N/A N/A
33698 MIG 7 系列和 Virtex-6 FPGA DDR2/DDR3 - 如何驱动用户接口? N/A N/A
AR# 34883
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP