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AR# 34902

Virtex-5 GTP Transceiver - "Warning: Input Clock Cycle-Cycle Jitter..."


The following warning message occurs while simulating supported GTP to DCM clocking setups:

"# Warning : Input Clock Cycle-Cycle Jitter on instance DEMO_TB.oc12_top_i.rxrecclk_dcm1_i.clock_divider_i.dcm_adv_1 exceeds 0.300 ns. Previous CLKIN Period = 12.832. Current CLKIN Period = 13.342."


This error can occur under supported clocking setups that have been tested by Xilinx to function in hardware. This can result in the DCM failing to lock and the output clocks being flat or invalid. Further, if these clocks supply TX or RX USRCLK and USRCLK2, RESETDONE might fail to assert.
AR# 34902
日期 03/24/2010
状态 Active
Type 综合文章