AR# 34923

MIG Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Design Signal and Parameter Descriptions

描述

This section of the MIG Design Assistant describes the signals and parameters for the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Core Architecture Signal and Parameter descriptions:
  • The User Interface signals and their descriptions can be found under the "Core Architecture" -> "User Interface" section in UG406.
  • The Native Interface signals and their descriptions can be found under the "Core Architecture" -> "Native Interface" section in UG406.
  • The Physical Interface signals and their descriptions can be found under the "Core Architecture" -> "Physical Interface" section in UG406.
  • The Configuration Parameters and their descriptions can be found under the "Customizing the Core" sections in UG406.
  • MIG Virtex-6 FPGA DDR2/DDR3 SDRAM Debug Signals and Parameter descriptions:
    • For a list of signals and parameters of interest for debugging simulations please check out the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs" -> "Simulation Debug" section in UG406.
    • The PHY Later Debug Signals and their descriptions can be found under the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Hardware Debug" -> PHY Layer Debug Port" section in UG406.

    Virtex-6 FPGA Memory Interface Solutions User Guide (UG406):
    http://www.xilinx.com/support/documentation/ipinterconnect_mig-v6s6.htm

    Additional Information
    (Xilinx Answer 40462) MIG 7 Series and Virtex-6 DDR2/DDR3 - How are CAS Latency (CL) and CAS Write Latency (CWL - DDR3 only) determined?

    链接问答记录

    主要问答记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    34243 Xilinx Memory Interface Solution Center N/A N/A

    子答复记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    43879 7 系列 MIG DDR3/DDR2 - 硬件调试指南 N/A N/A

    相关答复记录

    Answer Number 问答标题 问题版本 已解决问题的版本
    34905 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Reordering Memory Controller N/A N/A
    34718 MIG Virtex-6 DDR2/DDR3 - PHY Architecture N/A N/A
    AR# 34923
    日期 02/07/2013
    状态 Active
    Type 解决方案中心
    器件 More Less
    IP