AR# 34964

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Xilinx Virtex-6 FPGA Solution Center - Design Assistant

描述

The Virtex-6 FPGA Design Assistant walks you through the recommended design flow for Virtex-6 FPGA while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently with Virtex-6 FPGA.

NOTE: This answer record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

解决方案

First, select the design phase where you have a question or are troubleshooting an issue related to your Virtex-6 FPGA design. This ensures the Design Assistant points you to the information you need to move forward with your design.

(Xilinx Answer 34965) - Getting Started with the Virtex-6 FPGA
(Xilinx Answer 34977) - Designing for the Virtex-6 FPGA
(Xilinx Answer 37710) - Board Level Considerations
(Xilinx Answer 37211) - Troubleshooting - Clocking, Fabric, block RAM/FIFO

* For troubleshooting of other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

相关答复记录

AR# 34964
日期 02/07/2013
状态 Active
Type 解决方案中心
器件 More Less
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