AR# 35157


Serial RapidIO v5.5 - Release Notes and Known Issues for ISE 12.1 Design Tools


This Release Notes and Known Issues Answer Record is for the Serial RapidIO v5.5 Core, which was released in ISE 12.1 design tools and contains the following information:
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide:


New Features
  • ISE 12.1 design tools support
  • Designed to RapidIO Interconnect Specification v2.1
  • Virtex-6 LXT/HXT/SXT 5.0 Gb/s device support
  • Spartan-6 3.125 Gb/s and 4x device support
  • Expanded simulator support
  • Support for ML505, ML605 and SP605 boards (Xilinx Answer 29159)

Resolved Issues
  • PHY does not properly pass CRF bit to Buffer (CR# 519603)
  • GT settings for Spartan-6 and Virtex-6 FPGA updated based on characterization
  • Processing Element Features CAR implemented incorrectly. Part of the PEF CAR was implemented in the PHY configuration space, now it is merged into the LOGIO configuration space as directed by the spec. See core User Guide for map of configuration space.
  • (Xilinx Answer 34490) Port_initialized intermittently toggles
    (Xilinx Answer 33574) Recommended modifications to Example Design reset scheme
  • (Xilinx Answer 33527) Example design "implement.bat" file has error
  • (Xilinx Answer 32195) Virtex-4 FXT 3.125G, 4x core might not meet timing

Known Issues

Revision History
05/03/2010 - Initial Release
12/20/2010 - Additional Known Issues
12/03/2012 - Added (Xilinx Answer 53260) and (Xilinx Answer 53261)



AR# 35157
日期 12/03/2012
状态 Active
Type 版本说明
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