AR# 35165: 12.1 EDK - Why Does Base System builder allow me to create a design that has timing errors?
AR# 35165
12.1 EDK - Why Does Base System builder allow me to create a design that has timing errors?
描述
Why Does Base System builder allow me to create a design that has timing errors?
解决方案
Base System Builder does not guarantee timing if there are 9 slaves or more on the PLB bus. This problem has been noted for Virtex-6 FPGA designs running at 150 MHz.