AR# 35165

12.1 EDK - Why Does Base System builder allow me to create a design that has timing errors?

描述

Why Does Base System builder allow me to create a design that has timing errors?

解决方案

Base System Builder does not guarantee timing if there are 9 slaves or more on the PLB bus.  This problem has been noted for Virtex-6 FPGA designs running at 150 MHz.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34609 12.x EDK - 主要问答记录列表 N/A N/A
AR# 35165
日期 05/23/2014
状态 Archive
Type 综合文章
Tools