This Answer Record details how to debug a failure during the Write Leveling stage of the Virtex-6 MIG DDR3 calibration process.Write Leveling is only performed for DDR3 designs.For general details on Write Leveling, see (Xilinx Answer 35094).
NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enables.It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 34588).
NOTE: This Answer Record is part of the Xilinx MIG Solution Center. The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Write Leveling Failures (DDR3 Only)
Signals of Interest:
dgb_wrlvl_start = Memory Initialization Completed Successfully and Write Leveling Begins
dbg_wl_dqs_inverted = 1-bit value indicating whether the DQS output is inverted as a result of write leveling:
0: Not inverted
dbg_wl_odelay_dq_tap_cnt = IODELAY output tap count for all DQ and DM bits in each DQS group
dbg_wl_odelay_dqs_tap_cnt = IODELAY output tap count for each DQS
dbg_wl_edge_detect_valid = Asserts when an edge (transition) on DQ is detected (located in phy_wrlvl.v/.vhd module)
dbg_wl_state = Current state of Write Leveling state machine (located in phy_wrlvl.v/.vhd module)
Parameters of Interest:
WRLVL is the top-level rtl parameter that controls Write Leveling. This should be set to "ON" for ALL DDR3 designs. The MIG design always performs Write Leveling for DDR3 designs to calibrate the DQS-CK timing.
RTT_WR and RTT_NOM are top-level rtl parameters that control ODT. These must be set correctly for Write Leveling to complete successfully. MIG outputs the correct values based on the options selected in the MIG tool.
Files of Interest:
'rtl/phy/phy_wrlvl.v/lvhd' is the rtl module that contains the Write Leveling Logic.
What can go wrong?
Write Leveling fails if an edge is not detected on DQ (no assertion of dbg_wl_edge_detect_valid and saturation of dbg_wl_odelay_dqs_tap_cnt ). This can occur if DQS is not toggling.It is important to verify on the board that DQS is in fact toggling during Write Leveling.DQS is sent out by the FPGA during write leveling and is the clock input of a FF in the SDRAM. Therefore, if DQS is not toggling, DQ remains unchanged. Write Leveling must detect an edge on DQ for successful completion of the stage.The following factors should be analyzed to determine why an edge is not detected and/or DQS is not toggling.
Reference clock frequency is wrong. This results in an incorrect tap resolution and the write leveling algorithm would not calibrate properly.
The design is synthesized for high frequency, but runs at a slower frequency.Ensure the frequency synthesized is being run on the board.
IDELAYCTRLS are not properly instantiated due to pin-out changes. An IDELAYCTRL is a primitive required in any bank where IODELAYs are used. Any bank that includes DQ, DQS, the capture clock I/O logic, and the resynchronization clock I/O logic must include an IDELAYCTRL. FPGA Editor can be used to verify IDELAYCTRLs are LOCed in all MIG banks containing these pins.If the pin-out has been changed, refer to the Pin-Out and Banking Requirements section of the Design Assistant (Xilinx Answer 34308).
All bytes need to be working for write leveling to complete. A byte that returns no data stalls the algorithm.
MMCM is not running at or above 1 GHz.This increases jitter which could cause problems during Write Leveling.The MIG design requires the internal MMCM VCO frequency run at or above 1GHz. MIG sets the MMCM parameters appropriately to ensure this, however, if the input clock frequency has been modified, the VCO frequency might be below 1 GHz. Ensure the VCO frequency is running at or above 1 GHz.The MIG design sets all MMCM parameters in the MMCM instantiation in the output infrastructure.v/.vhd module.