AR# 35180: Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA
Spartan-6 - 12.4 Software Known Issues related to the Spartan-6 FPGA
This Answer Record describes the Known Issues for the Spartan-6 FPGA generation used with ISE Design Suite 12.
The following represent a collection of issues that have been identified in the12.4 ISE Design Tools and are related to Spartan-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.
It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device. This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in softwareare picked up.
IODELAY2: (Xilinx Answer 38408) Spartan-6 Design Advisory - IODELAY2 -early edge delays, late edge delays,and single data bit corruption
PCI Express: (Xilinx Answer 37955) Spartan-6 FPGA Integrated Block Wrapper v2.1 for PCI Express - VHDL Wrapper Not Available for v2.1 Release (Xilinx Answer 36416) Spartan-6 FPGA Integrated Block Wrapper v1.4 and v2.1 for PCI Express - User implemented configuration space registers starting addresses are not customizable
Timing Analysis: (Xilinx Answer 39545) 12.4 - Timing Analysis -ISE 12.4 does not support Spartan-6 -3 speed grade Engineering Sample (ES) devices
Revision History 12/20/2010 - Updated complete list for 12.4 Known Issues 10/05/2010 - Updated complete list for 12.3 Known Issues 07/23/2010 - Updated complete list for 12.2 Known Issues 06/16/2010 - Added Answer Records 35978, 35976, 35818, 35044, and 36221 05/19/2010 - Added "Additional Resources" section 05/03/2010 - Initial 12.1 Release