AR# 35209

MIG Virtex-6 DDR2/DDR3 - Isolating a Read vs. a Write Error


When calibration fails or data/bit errors are seen in hardware, it might be necessary to determine whether the issue is related to the write or read. This Answer Record focuses on how to determine whether the write or read is the root cause of the issue at hand.

NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enabled. It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 34588).

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Isolating whether data corruption is due to writes or reads can be difficult to determine because if writes are the cause, read back of the data is bad as well. In addition, issues with control or address timing affect both writes and reads.

Some experiments that can be tried to isolate the issue are:
  • If the errors are intermittent, have the controller issue a small initial number of writes, followed by continuous reads from those locations. If the reads intermittently yield bad data, there is a potential read problem.
  • Check/vary only write timing:
    • If on-die termination is used, check that the correct value is enabled in the DDR2/DDR3 device and that the timing on the ODT signal relative to the write burst is correct.
    • Use the Debug Port to change the post-calibration values of the write IODELAY taps for DQ and DQS. This allows the DQ and DQS write IODELAY taps to be decoupled. In normal operation, IODELAY (DQ) = IODELAY (DQS) 90
    • Procedure:
      1. Set dbg_wr_tap_set_en = 1
      2. Set DQS delay:
        • Set all bit fields of dbg_wr_dqs_tap_set to appropriate value
        • Each 5-bits of this vector corresponds to a DQS group
        • e.g., dbg_wr_dqs_tap_set[9:5] corresponds to DQS[1]
      3. Set DQ delay:
        • Repeat procedure for dbg_wr_dq_tap_set
        • Each 5-bits of this vector corresponds to the delays of all the DQ/DM bits in that DQS group
      • NOTE: Changing write timing is different than changing read capture timing the full 5-bit IODELAY value must be specified, rather than incrementing/decrementing one-tap at a time
  • Vary only read timing:
    • Check the IDELAY values after calibration. Look for variations between IDELAY values. IDELAY values should be very similar for DQs in the same DQS group.
    • Vary the IDELAY taps after calibration for the bits that are returning bad data. This affects only the read capture timing.
      • This process can also be used to determine read timing margin
    • Procedure
      1. Disable Phase Detector ongoing calibration - Set dbg_pd_maintain_off = 1
        • If the Phase Detector is not disabled, any changes made to the capture clock timing will be offset by the Phase Detector
      2. Set dbg_inc_dec_sel to select which DQS groups capture clock to adjust
        • Binary encoded e.g. dbg_inc_dec_sel[ ] = 0x02 corresponds to DQS[2]
      3. To increment or decrement by one IODELAY tap pulse either dbg_inc_cpt or dbg_dec_cpt for one CLK cycle (CLK = half-rate BUFG clock)
      4. New value reflected in appropriate field of dbg_cpt_tap_cnt
        • e.g., if dbg_inc_dec_sel[ ] = 0x02, then dbg_cpt_tap_cnt[14:10] reflects new value
      5. Debug Port can also be used to adjust DQS input timing in same manner
        • DQS is used by the phase detector
        • Used dbg_inc_dec_sel, dbg_inc_rd_dqs, dqs_dec_rd_dqs
For general information on how to use the Debug port, please see (Xilinx Answer 35206).



AR# 35209
日期 11/22/2016
状态 Active
Type 综合文章
器件 More Less