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AR# 35212

Design Assistant for PCI Express - How to capture Endpoint Block Plus Wrapper internal signals using ChipScope Inserter?


This Answer Record describes how tocapture Endpoint Block Plus Wrapper internal signals using ChipScope Inserter.
NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


Following are the steps to perform to capture signals with ChipScope inserter.

  1. After generating the core in CORE Generator, modify xst.scr in the implement directory to set KEEP_HIERARCHY to true.

    -ifn xilinx_pci_exp_1_lane_ep_inc.xst
    -ifmt Mixed
    -p xc5vlx50t-ff1136-2
    -bufg 0
    -top xilinx_pci_exp_ep
    -ofn xilinx_pci_exp_ep.ngc
    -opt_mode SPEED
    -opt_level 2
    -ofmt NGC
    -uc endpoint_blk_plus_v1_13.xcf
    -keep_hierarchy YES
  2. Run implement.bat/implement.sh depending on the operating system you are using.
  3. Once the synthesis is complete the ngc file called xilinx_pci_exp_ep.ngc is generated in the results directory inside the implement directory.
  4. Open ChipScope inserter and follow the steps as shown in the screen captures below:

    Select the Trigger Width as required:

    Select the "Data Width" and "Data Depth" as required:

    Double-click on any of the ports shown in red below:

    Click on appropriate section of the hierarchy to select the signals.

    Once trigger, data, and clock signals have been selected, click OK and then click Insert>.

  5. A new ".ngc" fileis generated with ChipScope core inside it, replacing the existing one.Before closing the ChipScope Inserter, save the project; a ".cdc" fileis generated. This ".cdc" file is required to view the signals in ChipScope Analyzer.
  6. Re-implement the design by running implement.bat/implement.sh. Make sure a section of the script with commands to synthesize has been removed.



Answer Number 问答标题 问题版本 已解决问题的版本
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 35212
日期 12/15/2012
状态 Active
Type 综合文章
  • Virtex-5 LXT
  • Virtex-5 TXT
  • Virtex-5 SXT
  • Endpoint Block Plus Wrapper for PCI Express