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AR# 35225

Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit VHDL Wrapper corrupts received TLP addresses

描述


Known Issue: v1.5, v1.4.3, v1.4.2, v1.4.1
Under some conditions received TLPs might have an incorrect address when using the x8 Gen 2 128-bit VHDL Wrapper.

解决方案


This issue is resolved in v1.5 rev 1.For the v1.5 rev 1 patch, see (Xilinx Answer 34279).
This problem does not exist in the Verilog version of the wrapper.
Revision History
07/14/2010 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35225
日期 05/20/2012
状态 Archive
Type 已知问题
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