AR# 35247

MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites

描述

Starting with MIG v3.4, MIG includes an option to support internal VREF. 

This is a Virtex-6 FPGA feature where using an internal VREF allows the VREF pins to be used for general-purpose I/O. 

This frees up two pins in a bank. 

MIG v3.4 also supports a Fixed Pin-Out tool where users can manually assign the interface pins to the user chosen pin locations. 

The tool then verifies the selected pins follow the MIG pin guidelines.

Please see the Virtex-6 Memory Interface Solutions User Guide for details on these two features.


When selecting pins in the Fixed Pin-Out tool, users should be able to assign pins to the VREF sites when the "Internal VREF" option is enabled on the FPGA Options screen. 

However, in MIG v3.4, the tool does not allow any pin selection on the VREF pin sites.

解决方案

This is an error in the Fixed Pin-Out tool and will be resolved in MIG v3.5 (available with ISE 12.2).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35247
日期 08/20/2014
状态 Active
Type 已知问题
器件 More Less
IP