When I implement with the v1.3 or v1.3 rev 1 core targeting ES silicon, or the v1.4, v1.4 rev 2 core targeting production silicon, there are problems with link training and device recognition on some platforms.
On a cold start, the endpoint is not recognized by the system and the endpoint does not link train.
If I issue a subsequent warm reset (Windows Restart), then the endpoint links train and is recognized.
In ISE Design Suite 11.5, the software automatically inserts the MMCM Calibration Circuit described in (Xilinx Answer 33849).
This circuit appears to cause issues with link training when using the v1.3 or v1.3 rev 1 wrapper on ES silicon, or the v1.4, v1.4 rev 2 wrapper on Production silicon.
This issue is fixed in the ISE Design Suite 12.1 release of the v1.5 wrapper for Production silicon.
For a solution for the v1.3 rev 1 core, see (Xilinx Answer 36008).
Revision History
06/08/2010 - Updated for v1.3 fix link.
05/03/2010 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 33276 | Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 | N/A | N/A |
| AR# 35426 | |
|---|---|
| 日期 | 02/20/2015 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |