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  3. AR# 35638: LogiCORE IP Video Scaler v2.1 - Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?

AR# 35638

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LogiCORE IP Video Scaler v2.1 - Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?

描述

Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?

解决方案

This is a known problem that only affects the pCore interface and is addressed in the next release of the Video On Screen Display IP.

You can contact Xilinx Technical Support for a way to work around this issue.

Please see (Xilinx Answer 31958) for a detailed list of LogiCORE IP Video Scaler Release Notes and Known Issues.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A
AR# 35638
日期 05/23/2014
状态 Archive
Type 综合文章
器件 More Less
IP
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