The table below includes updated values for PMA_RX_CFG for a variety of setups. These values have shown to be optimized for these situations:
Line Rate (Gbps) | Reference Clock Offset | PLL Output Divider | PMA_RX_CFG |
2.4 - 3.24 | 0 | 1 | 0x05CE004 |
1.2 - 1.62 | 0 | 2 | 0x05CE008 |
0.6 - 0.81 | 0 | 4 | 0x05CE008 |
2.4 - 3.24 | +/-200ppm | 1 | 0x05CE089 |
1.2 - 1.62 | +/-200ppm | 2 | 0x05CE049 |
0.6 - 0.81 | +/-200ppm | 4 | 0x05CE049 |
| AR# 35776 | |
|---|---|
| 日期 | 05/20/2010 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| IP | |