AR# 35783


Spartan-6 - How are the IODELAY2 tap delays calculated?


How do you calculate the tap delay in IOLDEAY2?


Calculating Delay
Unlike the Virtex architectures, there is no IDELAYCTRL in Spartan-6 devices, so the delay can vary over PVT.Because of this, the Spartan-6 Data Sheet (DS162), Table 38 indicates a maximum delay for each of the first 8 taps, and an equation to calculate the total maximum delay for any specified tap value:
Maximum delay = integer (number of taps/8) TTAP8 + TTAPn (where "n" equals the remainder)
Maximum Delay
To calculate the maximum tap value, use the total taps available of 256.This gives your maximum delay in the IODELAY2 of 13.57nS.
Minimum Delay
For minimum delay consult the TRACE setup and hold report.Note that the minimum delayis no less than 30% of the max delay.
The data sheet also gives a specification for the FMINCAL of the IODELAY2. It is defined as:
Minimum allowed bit rate for calibration in variable
The value for FMINCAL is 188Mb/s.The reason for this specification is that your bit period cannot exceed the total tap delay in the IODELAY2, since during calibration your tap delay line is set to the value of one bit period.Therefore, the minimum delay which is available to correlate to the minimum bit period allowed would be 1/188Mb/s or 5.32nS.This specification is essentially indicating that the minimum delay available in the IODELAY2 is 5.32nS.



Answer Number 问答标题 问题版本 已解决问题的版本
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 35783
日期 12/15/2012
状态 Active
Type 综合文章
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