AR# 35836

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LogiCORE IP 10-Gigabit Ethernet MAC - Timing errors seen when targeting Virtex-4 FPGAs

描述

In v8.5 and later of the LogiCORE IP 10-Gigabit Ethernet MAC, timing errors have been experienced in some Virtex-4 FPGA FPGA implementations.

解决方案

To resolve these errors, try removing the -timing switch from MAP or try using AREA_GROUP constraints. 

If timing failures are still encountered, open a webcase with Xilinx Technical Support to further explore a solution.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
35244 LogiCORE IP 10-Gigabit Ethernet MAC v10.1 - Release Notes and Known Issues for ISE Design Tools 12.1 N/A N/A
AR# 35836
日期 05/26/2014
状态 Archive
Type 综合文章
器件
Tools
IP
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