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AR# 35913

Design Assistant for PCI Express - Why does a single memory read request result in multiple completions?

描述

Why does a single memory read request result in multiple completions being returned?

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

解决方案

The PCI Express specification in section 2.3.1.1 details how completions for a single read request can be broken up. Any read larger than 64 bytes is almost always broken up into multiple completions and very often reads smaller than 64 bytes can be broken up depending on the starting address of the read. The user application must be able to handle this scenario.

For more information and the various rules that govern data returned for read request, see section 2.3.1.1 of the specification. Also,for information on ordering of completions, see (Xilinx Answer 36591).

Revision History:
02/21/2011 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 35913
日期 12/15/2012
状态 Active
Type 综合文章
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Virtex-5 Integrated Endpoint Block
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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