AR# 3595


NGDBuild - "logical block ' ' of type 'READBACK' is unexpanded" with a Synplify netlist


NGDBuild issues a warning on the instantiated READBACK component in your HDL:

"warning basnu:93-logical block 'rebk1' of type 'READBACK' is unexpanded."


Synplicity's Synplify incorrectly declares the READBACK symbol in the xc4000 libraries. The READBACK component is actually composed of two components: 1 RDBK and 1 RDCLK. If these two components are declared instead of READBACK, the design will be able to translate through NGDBuild. Another solution is to change the file extension from ".xnf" to ".sxnf". This performs a translation step of Synopsys understood components. Synplify borrows these Synopsys component names. So there are two work-arounds:

- declare RDBK and RDCLK


- change ".xnf" to ".sxnf" or ".edf" to sedif

NOTE: Instantiating the RDCLK indicates to the FPGA that the USER clock will be used for readback. If this is not the case, then only instantion of the RDBK is necessary, and the FPGA will use the onboard CCLK for readback.

-- XC4000e/ex/xl - READBACK VHDL code

library IEEE;

use IEEE.std_logic_1164.all;

library xc4000;

use xc4000.components.all;

entity rdbk_ex is

port (

rt, clk : in STD_LOGIC;

rd, rip_p : out STD_LOGIC


end rdbk_ex;

architecture xilinx of rdbk_ex is


U0: RDBK port map (TRIG => rt, DATA => rd, RIP => rip_p);

U1: RDCLK port map (I => clk);

end xilinx;

// XC4000e/ex/xl - READBACK Verilog code

`include "/path/to/synplify/lib/xilinx/xc4000.v"

module rdbk_ex (rt, clk, rd, rip_p);

input rt, clk;

output rd, rip_p;

RDBK U0 (.TRIG (rt), .DATA (rd), .RIP (rip_p));

RDCLK U1 (.I (clk));


AR# 3595
日期 05/14/2014
状态 Archive
Type 综合文章
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