We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35971

ISE 12.1 - CompXLib compiles both languages when only specifying one


When I run compxlib with -l vhdl and -lib all, -lib EDK, or no -lib option, both vhdl and verilog libraries are compiled even though only vhdl is specified.
Why is compxlib compiling both languages?


When you run Compxlib and compile the EDK Simulation libraries, it is required that both languages be compiled. The EDK simulation libraries are mixed languages and some cores only have one language, so both verilog and vhdl primitives need to be compiled.
AR# 35971
日期 12/15/2012
状态 Archive
Type 综合文章
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less