UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变. 万物智能.
  2. 技术支持
  3. AR# 35985: 12.1 EDK - ERROR:EDK - Ethernet_MAC (xps_ethernetlite) - expected integer but got ""

AR# 35985

12.1 EDK - ERROR:EDK - Ethernet_MAC (xps_ethernetlite) - expected integer but got ""

描述

After adding a mii_to_rmii core to an XPS project, and making the connections between xps_ethernetlite and the mii_to_rmii core, the following platgen error occurs:

ERROR:EDK - xget_value name : a null handle was provided
ERROR:EDK - Ethernet_MAC (xps_ethernetlite) - expected integer but got ""


How do I resolve this error?

解决方案

This problem is caused by irrelevant OFFSET IN/OUT constraints generated by the XPS_ETHERNETLITE TCL file, which assumes that the PHY signals will be connected to external I/O pins.

To resolve this issue:

1. Right-click on the core in the GUI, and select 'Make this IP local'
 
2. Open the core TCL file located at "Project Folder/pcore/xps_ethernetlite_v4_00_a/data/xps_ethernetlite_v2_1_0.tcl"
 
3. Comment out the following lines:
 

########################################################
### OFFSET IN and OFFSET OUT constraints on PHY Clocks
########################################################
set tx_clk [ xget_connected_global_ports $mhsinst "PHY_tx_clk"]
set rx_clk [ xget_connected_global_ports $mhsinst "PHY_rx_clk"]
set global_tx_clk_name [ xget_hw_name [lindex $tx_clk 0] ]
set global_rx_clk_name [ xget_hw_name [lindex $rx_clk 0] ]
#puts $outputFile "OFFSET = OUT 10.000 AFTER \"$global_tx_clk_name\";"
puts $outputFile "OFFSET = IN 6.000 BEFORE \"$global_rx_clk_name\";"
#########################################################


Note: These TCL commands are used to generate the OFFSET IN/OUT constraint for the tx and rx clk, which are not required when connected to a mii_to_rmii core still inside the FPGA.

4. After commenting these command out, re-generate the bitstream.
 
5. Refer to the following Answer Records for information on system-level constraints:

(Xilinx Answer 18997)
(Xilinx Answer 19112)

This issue is fixed in the AXI_Ethernetlite core through the addition of a parameter to suppress constraint generation, starting in EDK 12.3.

The XPS_Ethernetlite is not planned to be enhanced.
AR# 35985
日期 06/25/2014
状态 Active
Type 错误信息
Tools
IP
的页面