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AR# 36019

Virtex-6 FPGA Integrated Block for PCI Express - Coregen allows generating a x8 Gen 2 design for the XC6VLX550T-2; But this is not supported

描述

In ISE software 12.1, the v1.5 core allows the user to generate a x8 Gen 2 design for the XC6VLX550T-2. The problem is that x8 Gen 2 is not supported in this part for a -2 speedgrade. Implementing will likely result in timing failures.

解决方案

There is no workaround for this since there is no -3 speed grade currently available for this part.

Revision History
06/03/2010 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 36019
日期 05/20/2012
状态 Active
Type 已知问题
器件
Tools
IP
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