AR# 3641


A1.4, F1.4, MTI: VHDL Timing Simulation produces "Error: a positive value of WIDTH must be specified"


Keywords: WIDTH, ROC, ROC_V, time_sim.vhd, MTI, Model Technology,
V-System, Modelsim

Urgency: Medium

General Description: When using the Model Technology simulator to perform
an A1.4/F1.4 VHDL Timing Simulation, the following error can occur:

# ** Failure: *** Error: a positive value of WIDTH must be specified ***
# Time: 0 ns Iteration: 0 Instance: /testbench/uut/roc_ngd2vhdl



Add a Configuration Statement to you Testbench

For the A1.4/F1.4 software release, a new simulation cell was added to the
VHDL simulation library called ROC (Reset On Configuration). The purpose
of the ROC cell is to simulate the occurance of the power-on reset cycle
that is performed in the actual device upon completion of configuration.
The ROC cell is automatically placed in the timing netlist (time_sim.vhd)
for designs which do not contain a STARTUP block and have not selected the
-gp (Bring Global Reset out as a Port) switch for ngd2vhdl. The WIDTH
value that is specified in the error message is the pulse width or
duration of the power-on reset.

The WIDTH value must be specified in order to perform a timing simulation.
The suggested method to do this is by adding a configuration statement to
the design testbench in which initializes this value.

The following is an example configuration statement which can be appended
to a testbench:

CONFIGURATION Post_M1_simulation OF <entity_name_of_testbench> IS
FOR <architecture_name_of_testbench>
FOR <instance_name_given_for_design_in_testbench>:<entity_name_of_design>
generic map (WIDTH => 100 ns);
END Post_M1_simulation;

In the above example, replace all fields delimited within greater-than and
less-than signs (<>) with the appropriate names for the design being
simulated. An example value of 100 ns is shown. If it is desired to
truely mimic actual device power-on reset duration, enter the T(POR) value
for the particular device from the databook. If you desire a quicker
simulation, a lesser value can be enetered as long as the Minimum GSR
Pulse Width, T(MRW), value is not violated for the particular target
device. T(MRW) may also be found in the Xilinx Databook. Generally
100 ns is a safe value for all Xilinx FPGAs and CPLDs.

The testbench will need to be recompiled (VCOM) after making these changes
and the Model Technology simulator (VSIM) will need to be invoked using
the configuration name, Post_M1_simulation, as the design to load.


Bring Global Set/Reset out as a port

An alternative to adding the configuration statement to your testbench
would be to bring the global set/reset net out as a port. If the design
does not contain a STARTUP block and this switch is activated, M1 will
produce a netlist which contains a global set/reset port for simulation
purposes only. This port will not appear in the implemented design. Once
this is done, the global reset can be controlled by toggling the GSR port
either from the testbench file or directly from the simulator.

To have M1 create a global set/rest port:

If using the Design Manager GUI, select the "Bring Out Global Set/Reset
Net as a Port" switch within the Implementation edit Template -->
Interface, Simulation Data Options box.

If using the M1 tools from command-line, issue a -gp switch when running


Not Suggested

As a last resort, a method to initialize the WIDTH value of
the ROC is to hand edit the initialization value within the ngd2vhdl
produced netlist. This is not the suggested method since this edit would
need to be performed everytime a simulation netlist is re-generated but is
offered as an alternative.

To edit the WIDTH value, open the timing simulation netlist (generally
called time_sim.vhd) with a text editor and edit the Time value of the
following line within the ROC entity declaration (generally towards the
top of the netlist):

WIDTH : Time := 0 ns) ;

For instance, if a 100 ns power-on reset is desired, the timing simulation
netlist should look like the following:

entity ROC is
generic ( InstancePath: STRING := "*";
WIDTH : Time := 100 ns) ;
port( O : out std_ulogic := '1' ) ;
attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

After making this change, compile the simulation netlist and perform the
simulation as normal.


Simulation Patch for A1.4

If the simulation patch for A1.4 (Xilinx Solution 3739) is installed
on the system, a switch has been added to NGD2VHDL that no longer
requires the previous resolutions. For designs requiring a ROC (do
not contain global reset port or "Bring out global reset port"
switch is not enabled) a new command-line switch, -rpw, is required
that now specified the value of the Reset pulse for the ROC.

A sample command-line usage of this switch specifying a 100 ns reset
pulse is:

ngd2vhdl -w -rpw 100 design.nga

For Design Manager users, this switch may be added by using the
Custom Template feature. See (Xilinx Solution 1227) for details on
using the Custom feature of the Template Manager.

For information about this patch including how to obtain it, see
(Xilinx Solution 3739).
AR# 3641
日期 10/06/2008
状态 Archive
Type 综合文章
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