AR# 36477


MIG v3.5, Virtex-6 DDR3/QDRII+ - "ERROR:Place:911 - CONFIG DCI_CASCADE = "34,35" is not a valid constraint."


When I implement a Virtex-6 FPGA multi-controller output from MIG v3.5 (DDR3 and/or QDRII+) and the same Master Bank is selected for multiple controllers, the following error occurs in MAP:

ERROR:Place:911 - CONFIG DCI_CASCADE = "34,35" is not a valid constraint.

Why does this error occur and how do I resolve it?


When MIG generates the multi-controller UCF, a DCI_CASCADE constraint is provided for each controller. 

If the same Master Bank is selected for more than one controller, there will be two DCI_CASCADE constraints noting the same master bank.

This causes the error in the MAP tools.

To work around this issue, the DCI_CASCADE constraints in the MIG-provided UCF should be combined so that only one master bank is declared. 

The UCF can be found in both the 'example_design/par' and 'user_design/par' directories.

In the following example the master bank of 34 was selected for two controllers:


NOTE: Syntax : CONFIG DCI_CASCADE = "master slave1 slave2 ..";

The work-around is to combine these constraints as follows: 

CONFIG DCI_CASCADE = "34 32 35";

This issue is resolved in MIG v3.6 which is included with the ISE 12.3 release.

Revision History:
07/23/2010 - Initial Release

AR# 36477
日期 08/18/2014
状态 Active
Type 综合文章
器件 More Less
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