2. 技术支持
  3. AR# 3655: M1.4 MAP: FATAL_ERROR:x4kma:x4kmamerge.c:4429:1.145.12.5 - Missing signal on pin 10
  4. AR# 36553: MIG v3.5, Spartan-3A DSP DDR SDRAM - MAP fails on MIG output design when synthesized using Synplicity

AR# 36553

MIG v3.5, Spartan-3A DSP DDR SDRAM - MAP fails on MIG output design when synthesized using Synplicity

描述

When a MIG v3.5 Spartan3A-DSP design is synthesized using Synplicity, the design fails during the MAP phase of ISE tool implementation.

The MAP failure is due to the "rst_iob_out" component not being packed into an IOB.

This occurs because the clk180 signal is incorrectly pruned away in the "tocontroller" module.

This issue only exists for Spartan-3A DSP DDR designs where the CAS Latency equals 2.5 and the synthesis tool selected is Synplicity.

This issue exists in both Verilog and VHDL designs.

There are no issues with XST designs.

解决方案


To work around this issue, a syn_keep attribute must be added to the clk180 signal in the "*controller_0" module.

VHDL Work-around:
Add the following constraint in the *controller_0.vhd" module:

attribute syn_keep : boolean;
attribute syn_keep of clk180 : signal is true;

 
Verilog Work-around:
Update the following in the "*controller_0.v" module:

Existing code:

generate if(CAS_LAT_VAL == 3'b110) begin : FD_INST
(* IOB = "FORCE" *) FD rst_iob_out
(
.Q(rst_dqs_div_int),
.D(rst_dqs_div_d), .C(~clk)
)/* synthesis syn_useioff = 1 */;


Modified code:

wire clk180 /* synthesis syn_keep = 1 */;
assign clk180 = ~clk;
generate if(CAS_LAT_VAL == 3'b110) begin : FD_INST
(* IOB = "FORCE" *) FD rst_iob_out
(
.Q(rst_dqs_div_int),
.D(rst_dqs_div_d),
.C(clk180)
)/* synthesis syn_useioff = 1 */;

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
36211 MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 N/A N/A
AR# 36553
日期 08/12/2014
状态 Active
Type 综合文章
器件
IP