attribute syn_keep : boolean;
attribute syn_keep of clk180 : signal is true;
generate if(CAS_LAT_VAL == 3'b110) begin : FD_INST
(* IOB = "FORCE" *) FD rst_iob_out
(
.Q(rst_dqs_div_int),
.D(rst_dqs_div_d), .C(~clk)
)/* synthesis syn_useioff = 1 */;
wire clk180 /* synthesis syn_keep = 1 */;
assign clk180 = ~clk;
generate if(CAS_LAT_VAL == 3'b110) begin : FD_INST
(* IOB = "FORCE" *) FD rst_iob_out
(
.Q(rst_dqs_div_int),
.D(rst_dqs_div_d),
.C(clk180)
)/* synthesis syn_useioff = 1 */;
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
36211 | MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 | N/A | N/A |
AR# 36553 | |
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日期 | 08/12/2014 |
状态 | Active |
Type | 综合文章 |
器件 | |
IP |