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AR# 3663

Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R

Description

Keywords: xx, timing simulation

Urgency: hot

General Description:
Outputs of CORE Generator COREs containing ROM and/or RAM may
be XX in simulation.

解决方案

X's may be seen on the outputs of CORE Generator modules
containing ROM or RAM when the function generator inputs are
forced to GND or VCC (Constant Coefficient Multipliers, FIR
Filters,for example).

The problem is caused by a bug in the Xilinx Mapper v1.4.

A Patch to the v1.4 Mapper is available on the Xilinx FTP site.

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip


AR# 3663
创建日期 03/22/1998
Last Updated 04/25/2000
状态 Archive
Type 综合文章