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AR# 3684

FPGA Configuration: DONE Pin does not go HIGH...

Description

Keywords: configuration, xchecker, done

What causes the DONE pin to stay low?

解决方案

DONE goes high when the LCA configuration memory is full and the FPGA has received a LENGTH_COUNT number of CCLKs. If Done does not go high, this usually means that either the device has not filled its configuration memory, or has not received sufficient CCLKs, and you need to check the following:
Is INIT valid (HIGH) but DONE still LOW?
This implies that there is a problem with the physical loading of the data.

a) Is data appearing at DIN? If configuring in a master serial mode, check to see that the PROM is actually enabled, and that it is outputting data on its data pin.

b) The FPGA may not have received enough CCLK cycles. This is a common problem in peripheral mode and slave mode, as well as in daisy chain arrangements. In peripheral mode, the last two bits of each byte do not get clocked out until the next byte is written to the FPGA. In both slave and peripheral modes, you can rerun Makebits with the -lc = aligned_lc option to use in both slave and peripheral modes, and you can rerun Makebits with the -lc = aligned_lc option to use the aligned to length count length count calculation method. The length count alignment method will adjust length count so that length count is met on the first bit of the last byte in the bitstream. Using this method will ensure that you get enough configuration clocks to make the device complete the configuration process.

If you are configuring in slave mode and CCLK can be controlled, you can also try sending clocks until DONE goes high instead of sending some fixed number of clocks based on the default length count calculation method.

If you are configuring in peripheral mode, the fact that the last two bits of each byte do not get clocked through the FPGA until the next byte is written to the device can be overcome by writing an additional byte (11111111) to the device.

c) Do the first 40 bits out of DOUT match the first bits of DIN, starting with the preamble?
(The preamble will be FF20 for the .bit files, and FF04 for PROM files. In both cases, DOUT should appear as FF20.)

If there is any mismatch of bits between DIN and DOUT, check CCLK and DIN on an oscilloscope for noise, as this may corrupt the actual length count value. Noise on CCLK may cause double clocking of data bits. If a "1" in length count is double clocked, it may give you a length count that is up to 2^23 times the actual value.

d) If configuring in slave mode and CCLK can be controlled, keep sending clocks until DONE goes high instead of counting the number of clocks being sent. Sending additional configuration clocks after length count is met or DONE goes high does not harm the device. If you are using the XChecker cable, the number of CCLKs sent by the cable cannot be controlled; however, the cable always sends 25 additional clocks in excess of any given length by default.

e) Sometimes the Xchecker gives the following message:
"DONE pin did not go high."

Check the following:
1. Mismatch part specified in .bit file and device under test
2. D/P pin needs to have a 10-50K pull-up resistor.
3. Data contention w/PROM device.

AR# 3684
创建日期 08/21/2007
Last Updated 03/07/2007
状态 Active
Type 综合文章