AR# 37212

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Virtex-6 FPGA Design Assistant - Troubleshoot Common Clocking Problems

描述


The Answer Record helps guide you to solutions to common problems with Clocking in Virtex-6 FPGA designs.
NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGASolution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

解决方案


See the information regarding the Virtex-5 PLL in theClocking Debug Guide for Virtex-6 MMCM troubleshooting:
http://www.xilinx.com/support/troubleshoot/clocking_debug.htm
If you still have a problem after running through the suggestions, open a WebCase with Xilinx Technical Support:
http://www.xilinx.com/support/clearexpress/websupport.htm

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
37211 Virtex-6 FPGA Design Assistant - Troubleshooting N/A N/A
AR# 37212
日期 12/15/2012
状态 Archive
Type 综合文章
器件 More Less
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