This Answer Record helps guide you to solutions to common problems with the fabric resources in Virtex-6 FPGA designs.
Note: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).
The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.
Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.
Select from the following list of common fabric related problems.
Each Answer Record helps guide you to a solution.
| (Xilinx Answer 34120) | Inversion not pushed into Output FF input |
| (Xilinx Answer 32987) | What options are available that allow two SRL16s to be combined into one LUT Complex? |
| (Xilinx Answer 34164) | Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34963 | Xilinx Virtex-6 FPGA Solution Center | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34120 | 11.3 Virtex-6/-5 Pack - Inversion not pushed into Output FF input | N/A | N/A |
| 32987 | 11.1 MAP, Virtex-6/ Virtex-5/ Spartan-6 - What options are available that allow two SRL16s to be combined into one LUT Complex? | N/A | N/A |
| 34164 | Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software | N/A | N/A |
| 37211 | Virtex-6 FPGA Design Assistant - Troubleshooting | N/A | N/A |