AR# 37214


Virtex-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems


This Answer Record helps guide you to solutions to common problems with the block RAM and FIFO resources in Virtex-6 FPGA designs.

NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


Select from the followinglist of common block RAM or FIFO related problems.Each Answer Record helps guide you to a solution:

Refer to the suggestions below for suggestions that can be used to help debug issues relating to the Virtex-6 Block RAM or FIFO

  • Refer to the Virtex-6 Memory Resources User Guide and verify that your usage of the Block RAM or FIFO block is a legal configuration (
  • Run a behavioral simulation of the design and verify proper functionality of the Block RAM or FIFO.
  • Run a post-par timing simulation and verify proper functionality. If a failure occurs here, your design may not be properly constrained.
  • Also check the timing report to ensure all control signals are properly constrained and synchronous. Check the Xilinx Timing Solution Center (Xilinx Answer 40832) for more information on timing in a Xilinx FPGA design.
  • Insert ChipScope into your design and probe all the ports of the FIFO or Block RAM. ChipScope can be used to probe parts of your design in fabric and view these signals in real time in hardware. For more information on ChipScope, please visit the ChipScope product page at

If you still have a problem after running through the suggestions and debug techniques, pleaseopen up a WebCase through Xilinx Technical Support:



Answer Number 问答标题 问题版本 已解决问题的版本
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A


AR# 37214
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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