The CPLD Fitter may duplicate combinatorial logic (2 inpus OR gates) feeding control signals (CLK, SR, OE, CE) during multi-level optimization increasing the macrocell count.
解决方案
1
IF you run into this situation, you can resolve the issue in either of two ways.
1. Turn off multi-level logic optimization from the Advanced optimization tab in the Design Manager, XC9500 template. This may cause other optimization/fitting problems.
2. Use the KEEP attribute on the 2 inpit OR gates feeding the control logic. This is a better solution.
2
A fix is available for this problem in the latest CPLD Tools update available on the Xilinx Download Area: