AR# 37349

Spartan-6, IODELAY2 - What is Fmincal and how is it affected by SDR and DDR data rates?


The Fmincal specification is defined as:
"Minimum allowed bit rate for calibration in variable mode: VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX, and DIFF_PHASE_DETECTOR."
This information is available in the Spartan-6 FPGA Data Sheet (DS162):


The Fmincal specification is a requirement for the IODELAY2 in Variable Mode based on the longest bit period that the taps can calibrate to. For SDR data rates, the bit period is equal to the clock period, so the clock frequency can be 188 Mhz (5.3nS bit period). If using DDR, then the bit period is half of the CLK period, so the clock frequency can be as low as 94 Mhz and still meet the requirements of 5.3nS bit period.



Answer Number 问答标题 问题版本 已解决问题的版本
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 37349
日期 12/15/2012
状态 Active
Type 综合文章