Map introduces DRC problem by configuring a CLB for external feed back but failing to define the external signal. This results in warnings about configured CLB pins that have no signal attached:
WARNING:x4kdr:82 - Blockcheck: The pin "F1" on comp (mapped physical logic cell) "U18/PWMPHC0_D" is configured to be used but has no signal attached to it.
解决方案
This problem is fixed in the latest M1.4 Core Tools Patch available on the Xilinx Download Area: